We propose in table 1 the following algorithm for
simulating the fractional delay system where Input is the
input of the filter, Output is the output, and Delay
is the desired fractional delay. The state of the system is
; e, b, d and
i are intermediary values. The central loop is processed N
times, where N is one of the two integers verifying relation
(7). The last loop is needed only for time-varying
applications (this will be explained in section 3.3).
: Modular LIF algorithm
The signal to noise ratio due to round-off floating point errors in this algorithm increases with the filter's order, but it is now known to be less than -80dB in single precision arithmetic for filters of order less than 20 [Tassart and Depalle, 1996].
